Details

Autor(en) / Beteiligte

• Chang, Pei-Yao
• Lin, Tay-Jyi
• Wang, Jinn-Shyan
• Yu, Yen-Hsiang

Titel

A 4R/2W Register File Design for UDVS Microprocessors in 65-nm CMOS

Ist Teil von

• IEEE transactions on circuits and systems. II, Express briefs, 2012-12, Vol.59 (12), p.908-912

Ort / Verlag

New York: IEEE

Erscheinungsjahr

2012

Quelle

IEL

Beschreibungen/Notizen

• This brief presents a 4R/2W register file design for two-issue microprocessors with ultra-wide dynamic voltage scaling. A full-N separated read port has been proposed to save ~ 19% area and to improve 4.5 ~ 10.4 % performance of state-of-the-art 1P3N designs for subthreshold operations. In addition, a reconfigurable write scheme has been proposed to utilize the unused write port in the energy-efficient mode with single-issue execution for ~ 18% write noise margin improvement. A test chip has been designed and fabricated using the TSMC 65-nm GP process, of which a minimum operating voltage of 148 mV has been measured.