Details

Autor(en) / Beteiligte

• ANTONELLI, G. A
• JIANG, G
• SODA, E
• LINIGER, E
• COHEN, S
• DEMAREST, J
• TAGAMI, M
• VANDER STRATEN, O
• BAUMANN, F
• SHAVIV, R
• MOUNTSIER, T
• DIXIT, G
• PARK, K. J
• KARIM, I
• WU, W
• SHOBHA, H
• SPOONER, T

Titel

Synergistic combinations of dielectrics and metallization process technology to achieve 22 nm interconnect performance targets

Ist Teil von

• Microelectronic engineering, 2012-04, Vol.92, p.9-14

Ort / Verlag

Amsterdam: Elsevier

Erscheinungsjahr

2012

Link zum Volltext

Quelle

Alma/SFX Local Collection

Beschreibungen/Notizen

• An improvement in interconnect performance implies a reduction of the resistance-capacitance (RC) time constant. Instead of scaling the capacitance at each technology node through a reduction in the dielectric constant of the interlayer dielectric (ILD), the interconnect aspect ratios could be scaled holding the ILD fixed. In this case, the material properties of the ILD must be robust to process-induced damage and amenable to the creation of high aspect ratio features. In addition, a metallization scheme that can provide void free Cu fill in high aspect ratio features is required. Characterization, patterning, and integration results collected on such an ultra-low-k (ULK) ILD material and void free metallization is presented. A measured reduction in the resistance of a 22 nm node interconnect in this ILD was observed as a function of increasing aspect ratio. The copper seed deposition process, capable of enabling the fill of even higher aspect ratio features, is also discussed.