Details

Autor(en) / Beteiligte

• Warnock, J.
• Wendel, D.
• Aipperspach, T.
• Behnen, E.
• Cordes, R.A.
• Dhong, S.H.
• Hirairi, K.
• Murakami, H.
• Onishi, S.
• Pham, D.C.
• Pille, J.
• Posluszny, S.D.
• Takahashi, O.
• Huajun Wen

Titel

Circuit Design Techniques for a First-Generation Cell Broadband Engine Processor

Ist Teil von

• IEEE journal of solid-state circuits, 2006-08, Vol.41 (8), p.1692-1706

Ort / Verlag

New York, NY: IEEE

Erscheinungsjahr

2006

Quelle

IEEE Electronic Library Online

Beschreibungen/Notizen

• The Cell Broadband Engine (Cell BE) is a multicore system-on-chip (SoC), implemented in a 90-nm high-performance silicon-on-insulator (SOI) technology, and optimized, within the triple constraints of area, power, and performance, to run at frequencies in excess of 3 GHz. The large scale of the design (~75 million logic transistors, and about 750 000 latches and flip-flops), high-volume requirements, and the desire to support multiple manufacturing facilities dictated a need for very robust circuit practices, but at the same time, the high-frequency goal drove the use of more aggressive styles in certain critical regions of the design. This paper describes the local clock design, along with the various latches and flip-flops deployed, followed by a discussion of the circuit techniques used for the digital logic implementation, including special considerations for high-speed synthesized control logic, semi-custom and full-custom static circuit design and full-custom dynamic logic circuits. In addition, the synergistic processor element (SPE) circuit design is described, followed by the techniques and issues associated with the SRAM design. Finally, the methods used for electrical verification are described, these being an important part of the strategy for ensuring overall design robustness and first-silicon success