Details

Autor(en) / Beteiligte

• Papa, David
• Viswanathan, Natarajan
• Sze, Cliff
• Zhuo Li
• Gi-Joon Nam
• Alpert, Charles
• Markov, Igor L.

Titel

Physical Synthesis with Clock-Network Optimization for Large Systems on Chips

Ist Teil von

• IEEE MICRO, 2011-07, Vol.31 (4), p.51-62

Ort / Verlag

Los Alamitos: IEEE

Erscheinungsjahr

2011

Quelle

IEEE/IET Electronic Library (IEL)

Beschreibungen/Notizen

• In traditional physical-synthesis methodologies, the placement of flip-flops and latches is problematic, especially for large systems on chips. A next-generation electronic-design-automation methodology improves timing closure through clock-network synthesis and placement of flip-flops and latches to avoid timing disruptions or immediately recover from them. When evaluated on large CPU designs, the methodology saw double-digit improvements in timing, wirelength, and area versus current technology.