Details

Autor(en) / Beteiligte

• Pence, William Edward

Titel

Electrical, thermal, and architecture aspects of VLSI packaging and interconnects for high-speed digital computers

Ort / Verlag

ProQuest Dissertations & Theses

Erscheinungsjahr

1989

Quelle

ProQuest Dissertations & Theses A&I

Beschreibungen/Notizen

• Packaging and interconnects for Very Large Scale Integration (VLSI) integrated circuits have become problematic as chip power levels, Input/Output (I/O) counts, and signal speeds have increased. This work addresses several important aspects of the packaging/interconnect problem in four major parts. In the first part, an analysis of the fundamental performance limitations imposed by system packaging is presented. With this approach, the importance of each limit is assessed for all levels of packaging. Following this discussion, three critical packaging problems-simultaneous switching ($\Delta$-I) noise, large interconnect delays, and high I/O counts (Rent's rule), are examined. In part two, the effect of package geometry on thermal resistance is studied for a group of conventional and novel packages. Thermal resistance is determined using electrothermal networks (variation of finite difference method) for free convection, forced air, forced liquid, and microchannel cooling. Thermal resistance is computed for each package and charted for each of the cooling methods mentioned above. The third part of this work is dedicated to a description of a new hierarchical model for an idealized digital electronic system. This model permits quantitative simulations of packaging performance. Since the model is comprehensive, including all technology levels from the circuit level to the machine architecture level, there exists the potential for examining difficult tradeoff issues. Questions of optimum hardware design are addressed using simulated annealing techniques. The fourth and final section of this work details the design, fabrication, and testing of a new glass-ceramic multichip module test vehicle. This effort is intended to determine the electrical, thermal, and materials properties of a new glass-ceramic material, and to assess the utility of this material in a multichip module technology. Design, layout, silicon test chip processing, and electrical testing are described in detail. Test results demonstrate improved signal propagation speed, noise properties, and chip-to-substrate thermal mismatch relative to conventional packaging materials.