Details

Autor(en) / Beteiligte

• Lin, Jia-Zhao
• Chen, Po-Ta
• Chin, Hung-Yuan
• Tsai, Pei-Yun
• Lee, Sz-Yuan

Titel

Design and Implementation of a Real-Time Imaging Processor for Spaceborne Synthetic Aperture Radar With Configurability

Ist Teil von

• IEEE transactions on very large scale integration (VLSI) systems, 2024-04, Vol.32 (4), p.669-681

Ort / Verlag

New York: IEEE

Erscheinungsjahr

2024

Quelle

IEEE/IET Electronic Library (IEL)

Beschreibungen/Notizen

• A real-time imaging processor for spaceborne synthetic aperture radar (SAR) is designed and implemented to realize the range Doppler algorithm (RDA) with configurability. The azimuth fast Fourier transform (FFT) decomposition is adopted for full utilization of data after fetching them from high bandwidth memory (HBM) by burst access to achieve streaming input-output for 2-D FFT/inverse FFT (IFFT) processing in all modes. Hybrid datapaths including fixed-point (FP), customized floating-point (CFP), and double-precision (DP) representations are used to achieve the desired signal-to-quantization-noise ratio (SQNR). The 2-D decoupling and scheduling technique is used for complexity reduction of computing spatially varying phase compensation terms. Besides, a multisegment second-order Taylor series expansion is proposed to approximate the migration factor for configurability, which is an essential component in cross-coupling compensation and azimuth compression (AC), especially when squint angle becomes large. Variable range FFT sizes from 8K to 32K are supported to cover different swath widths. The processing times for image sizes of 8K <inline-formula> <tex-math notation="LaTeX">\times8\text{K} </tex-math></inline-formula>, 8K <inline-formula> <tex-math notation="LaTeX">\times16\text{K} </tex-math></inline-formula>, and 8K <inline-formula> <tex-math notation="LaTeX">\times32\text{K} </tex-math></inline-formula> are 0.34, 0.68, and 1.35 s, respectively, which meet the real-time processing requirement. Our implementation demonstrates significant improvement in processing efficiency and hardware efficiency with configurability compared with prior works.