Details

Autor(en) / Beteiligte

• Xu, Yi-Nan
• Yu, Zi-Hao
• Wang, Kai-Fan
• Wang, Hua-Qiang
• Lin, Jia-Wei
• Jin, Yue
• Zhang, Lin-Juan
• Zhang, Zi-Fei
• Tang, Dan
• Wang, Sa
• Shi, Kan
• Sun, Ning-Hui
• Bao, Yun-Gang

Titel

Functional Verification for Agile Processor Development: A Case for Workflow Integration

Ist Teil von

• Journal of computer science and technology, 2023-07, Vol.38 (4), p.737-753

Ort / Verlag

Singapore: Springer Nature Singapore

Erscheinungsjahr

2023

Link zum Volltext

Quelle

Alma/SFX Local Collection

Beschreibungen/Notizen

• Agile hardware development methodology has been widely adopted over the past decade. Despite the research progress, the industry still doubts its applicability, especially for the functional verification of complicated processor chips. Functional verification commonly employs a simulation-based method of co-simulating the design under test with a reference model and checking the consistency of their outcomes given the same input stimuli. We observe limited collaboration and information exchange through the design and verification processes, dramatically leading to inefficiencies when applying the conventional functional verification workflow to agile development. In this paper, we propose workflow integration with collaborative task delegation and dynamic information exchange as the design principles to effectively address the challenges on functional verification under the agile development model. Based on workflow integration, we enhance the functional verification workflows with a series of novel methodologies and toolchains. The diff-rule based agile verification methodology (DRAV) reduces the overhead of building reference models with runtime execution information from designs under test. We present the RISC-V implementation for DRAV, DiffTest, which adopts information probes to extract internal design behaviors for co-simulation and debugging. It further integrates two plugins, namely XFUZZ for effective test generation guided by design coverage metrics and LightSSS for efficient fault analysis triggered by co-simulation mismatches. We present the integrated workflows for agile hardware development and demonstrate their effectiveness in designing and verifying RISC-V processors with 33 functional bugs found in N ut S hell . We also illustrate the efficiency of the proposed toolchains with a case study on a functional bug in the L2 cache of X iang S han .