Details

Autor(en) / Beteiligte

• Choi, Sureum
• Han, Daejin
• Choi, Chanyeong
• Seo, Yeongkyo

Titel

Layout-Aware Area Optimization of Transposable STT-MRAM for a Processing-In-Memory System

Ist Teil von

• IEEE transactions on very large scale integration (VLSI) systems, 2024-02, Vol.32 (2), p.1-11

Ort / Verlag

New York: IEEE

Erscheinungsjahr

2024

Quelle

IEEE Electronic Library (IEL)

Beschreibungen/Notizen

• This article presents a layout-aware area optimization methodology for transposable spin-transfer torque magnetic random access memory (STT-MRAM). Although transposable STT-MRAM achieves high performance in processing-in-memory (PIM) systems for a spiking neural network (SNN), challenges in layout design and optimization remain owing to the vertical arrangement of its two wordlines (WLs). We propose three different layout design techniques to address these challenges. We also analyze the cell area changes of our proposed layout design according to the width of two access transistors. The proposed layout designs for transposable STT-MRAM are implemented in a 28-nm CMOS technology coupled with a SPICE-compatible model for a magnetic tunnel junction. Results show that in the metal pitch limited region, our proposed perpendicular poly with metal column-WL-based layout design achieves minimum cell area, with at least 5.3% area savings in comparison with other proposed layout designs. Furthermore, by targeting an identical design specification of 35% write margin (WM) and 160% cell tunnel magnetoresistance, the resulting cell area falls in the transistor width-limited region. In this case, our proposed parallel poly with metal-WL-based layout design achieves at least 21% area savings compared with the other proposed layout designs. This result demonstrates that our proposed layout design and analysis offer valuable insights for circuit designers in selecting the optimal design that meets target specifications and requirements.