Details

Autor(en) / Beteiligte

• Chuang, Meng‐Hsi
• Chiu, Kuan‐Chang
• Lin, Yu‐Ting
• Tulevski, George
• Chen, Po‐Han
• Pezeshki, Atiye
• Chen, Chung‐Jen
• Chen, Po‐Yen
• Chen, Lih‐Juann
• Han, Shu‐Jen
• Lee, Yi‐Hsien

Titel

Integrated Low‐Dimensional Semiconductors for Scalable Low‐power CMOS Logic

Ist Teil von

• Advanced functional materials, 2023-07, Vol.33 (27), p.n/a

Ort / Verlag

Hoboken: Wiley Subscription Services, Inc

Erscheinungsjahr

2023

Quelle

Wiley-Blackwell Journals

Beschreibungen/Notizen

• Scalable nanoelectronics with energy‐efficient logic technology is crucial for next‐generation edge devices. Low‐dimensional semiconductors, such as transition metal dichalcogenides and single‐walled carbon nanotubes (SWCNTs), have tunable properties with reduced short‐channel effects. The unique properties of each material can be utilized owing to the heterogeneous integration of multiple semiconducting channels to form complementary metal‐oxide‐semiconductor (CMOS) logic. However, the integration remains challenging. This study reveals the realization of low static power hetero‐CMOS inverters by the integration of n‐type monolayer MoS2 and p‐type SWCNT networks. The balanced inverter exhibits a large peak gain of ≈67 at a supply voltage of 2 V with the customized design of the wafer‐scale synthetic process and channel integration. An ultralow standby power consumption of ≈5 pW and a practical peak gain of ≈7 at a reduced supply voltage of 0.25 V are achieved. A high noise margin (>70%) validates the circuit's tolerance to external noises and the dynamic analysis of the inverting amplifier in push–pull configuration exhibits a large AC gain. This work paves the way toward the wafer‐scale integration of low‐dimensional materials for low‐power nanoelectronics. Wafer‐scale low‐power hetero‐CMOS inverters are realized by integrating monolayer MoS2 and SWCNT networks. An ultralow standby power consumption of ≈5 pW at a reduced supply voltage of 0.25 V, high NMs (>70%), and dynamic analysis in a push‐pull configuration are achieved. It paves the way toward the wafer‐scale integration of low‐dimensional materials for low‐power nanoelectronics.