Details

Autor(en) / Beteiligte

• Minakshi Sanadhya, Minakshi Sanadhya
• Minakshi Sanadhya, Devendra Kumar Sharma

Titel

Adiabatic Logic Based Energy Efficient Architecture of 1-Bit Magnitude Comparator for IOT Applications

Ist Teil von

• Wangji Wanglu Jishu Xuekan = Journal of Internet Technology, 2022-01, Vol.23 (7), p.1643-1649

Ort / Verlag

Hualien: National Dong Hwa University, Computer Center

Erscheinungsjahr

2022

Quelle

Alma/SFX Local Collection

Beschreibungen/Notizen

• The Internet of Things (IoT) applies the sensors and microcontrollers and links them through the internet. The eventual objective of low-power devices for Internet of Things is to lesser the overall system power and to extend battery life. For the development of energy efficient IoT devices, novel adiabatic techniques are proposed. By improving the performance of the comparator, one can improvise the whole system performance. The efficacy of computing devices depends on the performance of arithmetic circuits, including comparator. This paper proposes 1-bit comparator design using adiabatic techniques such as DC-DB PFAL (Direct current diode-based positive feedback adiabatic logic) and MPFAL (Modify positive feedback adiabatic logic) which are well-suited with an extensive range of applications (e.g. IoT sensors and an inbuilt analog to digital converter). For performance analysis, the results are compared together along with the other adiabatic and non adiabatic designs already reported in the literature. This paper proposes a way to decrease the dissipation of power and transistor count in binary circuits as it is one of the primary concerns. From the results, it is found that the design using DC-DB PFAL logic shows an improvement in power-delay-product of 69%, 94% and 90% compared to MPFAL, PFAL and ECRL techniques respectively.