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Electronics (Basel), 2022-02, Vol.11 (3), p.328
2022
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Autor(en) / Beteiligte
Titel
Small Group Delay Variation and High Efficiency 3.1–10.6 GHz CMOS Power Amplifier for UWB Systems
Ist Teil von
  • Electronics (Basel), 2022-02, Vol.11 (3), p.328
Ort / Verlag
Basel: MDPI AG
Erscheinungsjahr
2022
Quelle
EZB Electronic Journals Library
Beschreibungen/Notizen
  • A two-stage cascaded power amplifier (PA) employing a proposed Resistor-Capacitor (RC) interstage was provided and simulated. The current-reuse topology is employed at the first stage to lower the power consumption, while the RC interstage helps to enrich the gain flatness and the wideband matching. The shunt peaking topology in a common source configuration is adopted at the second stage to enhance the power gain. The postlayout simulation is performed using the TSMC 65 nm CMOS process operating in a frequency band of 3.1 GHz to 10.6 GHz. The postlayout simulation results indicate that a high flat gain of approximately 22.8 ± 1.2 dB, small group delay variation of ±50 ps, and good input and output matching of less than −10 dB are achieved over the desired working band. Moreover, a saturated output power of 10 dBm and maximum power-added efficiency (PAE) of 29.5% is achieved at 6 GHz. The proposed PA consumes the low power of 15.5 mW from 1.2 V supply voltage.
Sprache
Englisch
Identifikatoren
ISSN: 2079-9292
eISSN: 2079-9292
DOI: 10.3390/electronics11030328
Titel-ID: cdi_proquest_journals_2627465430

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