Details

Autor(en) / Beteiligte

• Gao, Han
• Chen, Xu
• Esenlik, Semih
• Chen, Jianle
• Steinbach, Eckehard

Titel

Decoder-Side Motion Vector Refinement in VVC: Algorithm and Hardware Implementation Considerations

Ist Teil von

• IEEE transactions on circuits and systems for video technology, 2021-08, Vol.31 (8), p.3197-3211

Ort / Verlag

New York: IEEE

Erscheinungsjahr

2021

Link zum Volltext

• IEEE_Xplore

Quelle

IEEE Xplore

Beschreibungen/Notizen

• This paper presents an overview of the decoder-side motion vector refinement (DMVR) algorithm in the Versatile Video Coding (VVC) standard. The proposed DMVR algorithm aims to increase the prediction accuracy of the blocks coded in merge mode using the bilateral matching-based refinement method. Compared with previous decoder-side motion vector derivation approaches, the proposed method significantly increases the coding efficiency without signaling additional side information. Furthermore, the hardware implementation considerations of the DMVR design are particularly focused in this study. This paper details and analyzes the novel features of DMVR contributing to the increase in coding efficiency and the reduction in computational complexity and implementation difficulty. Experimental results based on the VVC test model version 8.0 demonstrate that average Bjøntegaard Delta rate savings of 0.80 % and 2.81 % are achieved for the "tool-off" and "tool-on" test configurations, respectively. Moreover, 4 % additional decoding time and negligible additional external memory bandwidth requirements of DMVR based on the common test conditions for VVC are reported.