Details

Autor(en) / Beteiligte

• Ramkaj, Athanasios T.
• Pena Ramos, Juan C.
• Pelgrom, Marcel J. M.
• Steyaert, Michiel S. J.
• Verhelst, Marian
• Tavernier, Filip

Titel

A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog-Digital Corrections in 28-nm CMOS

Ist Teil von

• IEEE journal of solid-state circuits, 2020-06, Vol.55 (6), p.1553-1564

Ort / Verlag

New York: IEEE

Erscheinungsjahr

2020

Link zum Volltext

• IEEE_Xplore

Quelle

IEEE Xplore Digital Library

Beschreibungen/Notizen

• This article presents a 5-GS/s 12-b passive-sampling <inline-formula> <tex-math notation="LaTeX">8\times </tex-math></inline-formula>-interleaved hybrid analog-to-digital converter (ADC) that achieves a low-frequency SFDR/SNDR of 75.2/62.4 dB and a Nyquist SFDR/SNDR of 65.4/58.5 dB. A significant power reduction while attaining a bandwidth in excess of 6 GHz and a high spectral purity are enabled by: 1) an on-chip terminated very fast settling buffer-less input front end; 2) an on-chip clock chain with as low as 11-fs added jitter; 3) an asynchronous three-stage pipelined-successive approximation register (SAR) sub-ADC; and 4) on-chip co-designed analog-digital calibrations deal with sub-ADC and time-interleaving (TI) artifacts to achieve the desired spectral performance levels. The 28-nm bulk CMOS prototype chip occupies a total area of 4.56 mm 2 with a core area of 1.76 mm 2 and consumes 158.6 mW from a 1-V supply, leading to the Nyquist figure of merits of Schreier (FoM S ) and Walden (FoM W ) of 160.5 dB and 46.1 fJ/conversion step, respectively.