Details

Autor(en) / Beteiligte

• Ortega‐Cabezas, Pedro Miguel
• Colmenar‐Santos, Antonio
• Borge‐Diez, David
• Blanes‐Peiró, Jorge Juan

Titel

Application of rule‐based expert systems in hardware‐in‐the‐loop simulation case study: Software and performance validation of an engine electronic control unit

Ist Teil von

• Journal of software : evolution and process, 2020-01, Vol.32 (1), p.n/a

Ort / Verlag

Chichester: Wiley Subscription Services, Inc

Erscheinungsjahr

2020

Quelle

Access via Wiley Online Library

Beschreibungen/Notizen

• Innovative techniques to validate software are needed to reduce cost and increase software quality. This research aims to check if two rule‐based expert systems (EXs) combined with dynamic‐link libraries (dlls) perform better than other techniques widely employed in the automotive sector when validating the engine electronic control unit (ECU) software by using a hardware‐in‐the‐loop (HIL) simulation. To perform this research, 15 software modules (SMs) of different complexities were chosen to be validated in an HIL simulation by using different techniques such as the manual execution, the tester‐in‐the‐loop, the model‐based testing, a rule‐based EX, and the combination of two EXs to establish the code and functional coverage, the productivity gain, the number of bugs found, potential limitations of each technique, and the success rate of the HIL simulation. The test cases used are described in‐depth in Section 2. The enhancement, which dlls and EXs offer, depends on the number of states in the functional model used in the EXs and the number of subintervals in which the SM inputs can be divided. A range between 6 and 16 more bugs can be detected when using two EXs. The HIL enhancement can reach 6%, 16.8%, and 18% depending on the SM complexity. This research used two rule‐based expert systems working in cooperation to assess the software and functional coverage when validating engine control unit software. This technique shows a better performance when searching for software and performance bugs in a hardware‐in‐the‐loop simulation regarding other techniques such as the tester‐in‐the‐loop or the model‐based testing. Its implementation is also compatible with the time frame of an engine project.