IEEE journal of solid-state circuits, 2020-01, Vol.55 (1), p.178-188
- Shibata, Noboru
- Kanda, Kazushige
- Shimizu, Takahiro
- Nakai, Jun
- Nagao, Osamu
- Kobayashi, Naoki
- Miakashi, Makoto
- Nagadomi, Yasushi
- Nakano, Tomoaki
- Kawabe, Takahisa
- Shibuya, Taira
- Sako, Mario
- Yanagidaira, Kosuke
- Hashimoto, Toshifumi
- Date, Hiroki
- Sato, Manabu
- Nakagawa, Tomoki
- Musha, Junji
- Minamoto, Takatoshi
- Uda, Mizuki
- Nakamura, Dai
- Sakurai, Katsuaki
- Yamashita, Takahiro
- Zhou, Jieyun
- Tachibana, Ryoichi
- Takagiwa, Teruo
- Sugimoto, Takahiro
- Ogawa, Masatsugu
- Ochi, Yusuke
- Kawaguchi, Kazuaki
- Kojima, Masatsugu
- Ogawa, Takeshi
- Hashiguchi, Tomoharu
- Fukuda, Ryo
- Masuda, Masami
- Kawakami, Koichi
- Someya, Tadashi
- Kajitani, Yasuyuki
- Matsumoto, Yuuki
- Sato, Jumpei
- Raghunathan, Namasivayam
- Koh, Yee Lih
- Chen, Shuo
- Lee, Juan
- Nasu, Hiroaki
- Sugawara, Hiroshi
- Hosono, Koji
- Hisada, Toshiki
- Nakamura, Hiroshi
2020
Volltextzugriff (PDF)
Details
- Autor(en) / Beteiligte
- Shibata, Noboru
- Kanda, Kazushige
- Shimizu, Takahiro
- Nakai, Jun
- Nagao, Osamu
- Kobayashi, Naoki
- Miakashi, Makoto
- Nagadomi, Yasushi
- Nakano, Tomoaki
- Kawabe, Takahisa
- Shibuya, Taira
- Sako, Mario
- Yanagidaira, Kosuke
- Hashimoto, Toshifumi
- Date, Hiroki
- Sato, Manabu
- Nakagawa, Tomoki
- Musha, Junji
- Minamoto, Takatoshi
- Uda, Mizuki
- Nakamura, Dai
- Sakurai, Katsuaki
- Yamashita, Takahiro
- Zhou, Jieyun
- Tachibana, Ryoichi
- Takagiwa, Teruo
- Sugimoto, Takahiro
- Ogawa, Masatsugu
- Ochi, Yusuke
- Kawaguchi, Kazuaki
- Kojima, Masatsugu
- Ogawa, Takeshi
- Hashiguchi, Tomoharu
- Fukuda, Ryo
- Masuda, Masami
- Kawakami, Koichi
- Someya, Tadashi
- Kajitani, Yasuyuki
- Matsumoto, Yuuki
- Sato, Jumpei
- Raghunathan, Namasivayam
- Koh, Yee Lih
- Chen, Shuo
- Lee, Juan
- Nasu, Hiroaki
- Sugawara, Hiroshi
- Hosono, Koji
- Hisada, Toshiki
- Nakamura, Hiroshi
- Titel
- A 1.33-Tb 4-Bit/Cell 3-D Flash Memory on a 96-Word-Line-Layer Technology
- Ist Teil von
- IEEE journal of solid-state circuits, 2020-01, Vol.55 (1), p.178-188
- Ort / Verlag
- New York: IEEE
- Erscheinungsjahr
- 2020
- Quelle
- IEL
- Beschreibungen/Notizen
- A 1.33-Tb 4-bit/cell quadruple-level (QLC) 3-D flash memory in a 96-word-line (WL)-layer technology that achieves 8.5 Gb/mm 2 has been developed. This is the biggest capacity and the highest bit density ever reported. A source-bias-negative-sense with CLK-control allows deep negative V th sensing while maintaining low supply voltage. A new two-step (8-16) programming method and VDD generator enhancement realized a narrow Vth for QLC with 18% tProg improvement. Page/state-dependent word-line (WL) overdrive shortens the WL transient time by 8%. An independent plane read enables reading from different WL address from each plane in multi-plane operation. Besides, mixing selection of QLC pages (lower/middle/upper/top) in one plane and triple-level cell (TLC) pages (lower/middle/upper) or single-level cell (SLC) page in the other is also supported to provide flexibility for system implementation.
- Sprache
- Englisch
- Identifikatoren
- ISSN: 0018-9200eISSN: 1558-173XDOI: 10.1109/JSSC.2019.2941758Titel-ID: cdi_proquest_journals_2332192789
- Format
- –
- Schlagworte
- 1-bit/cell single-level cell (SLC), 2-bit/cell multi-level cell (MLC), 3-bit/cell triple-level cell (TLC), 3-D flash memory, 4-bit/cell quadruple-level (QLC), and SLC, Bit error rate, Couplings, enhancement of VDD generator, Flash memories, Flash memory (computers), Generators, independent plane read (IPR), Intellectual property, mixed use of QLC, page/state-dependent word-line (WL) over-drive, Programming, Reliability, source-bias-negative-sense (SBNS), TLC