Details

Autor(en) / Beteiligte

• Dinis, Daniel C.
• Ma, Rui
• Shinjo, Shintaro
• Yamanaka, Koji
• Teo, Koon Hoo
• Orlik, Philip V.
• Oliveira, Arnaldo S. R.
• Vieira, Jose

Titel

A Real-Time Architecture for Agile and FPGA-Based Concurrent Triple-Band All-Digital RF Transmission

Ist Teil von

• IEEE transactions on microwave theory and techniques, 2018-11, Vol.66 (11), p.4955-4966

Ort / Verlag

New York: IEEE

Erscheinungsjahr

2018

Quelle

IEEE Electronic Library Online

Beschreibungen/Notizen

• Contiguous/noncontiguous carrier aggregation (CA) is one of the key features from 4G systems, which is expected to be evolved within 5G technologies. Thus, there is a need for the development of flexible, agile, and reconfigurable radio transceivers with a native support for the integration of multiple bands and multiple standards. All-digital radio-frequency (RF) transmitters have demonstrated promising potential to the design of next-generation RF transceivers. However, the simultaneous multiband transmission is still one of the key limitations of current approaches. To address this problem, this paper presents a fully digital and parallel architecture that enables the real-time design of agile and concurrent triple-band transmission. The proposed architecture is suitable for both contiguous and noncontiguous CA scenarios and considerably surpasses the state of the art in terms of frequency agility, maximum spacing between bands, and aggregated bandwidth. To enhance the system performance, an extension to a multilevel architecture based on the analog combination of pulsed waveforms is also demonstrated. Both architectures (two and seven levels) were implemented in a field-programmable gate array. Measurement results in terms of signal-to-noise ratio, error-vector magnitude, and adjacent-channel power ratio are presented and discussed. In Implementation-I, the two-level architecture presents a frequency agility from 0.1 to 2.5 GHz (with a frequency resolution of 4.88 MHz) with an aggregated bandwidth of 56.26 MHz. In Implementation-II, the seven-level design presents a frequency agility from 0.1 to 2 GHz (with a frequency resolution of 3.906 MHz) with an aggregated bandwidth of 112.5 MHz.