Details

Autor(en) / Beteiligte

• Nidhi, Karuna
• Ming-Dou Ker

Titel

A CMOS-Process-Compatible Low-Voltage Junction-FET With Adjustable Pinch-Off Voltage

Ist Teil von

• IEEE transactions on electron devices, 2017-07, Vol.64 (7), p.2812-2819

Ort / Verlag

New York: IEEE

Erscheinungsjahr

2017

Link zum Volltext

• IEEE_Xplore

Quelle

IEEE Electronic Library (IEL)

Beschreibungen/Notizen

• A novel horizontal n-channel junction field-effect transistor (n-JFET) device is proposed and verified in a 0.25-μm bulk CMOS process. This horizontal JFET consists of alternating n-and p-regions formed by using the P-type electro-static discharge (ESD) implantation. P-type ESD implantation has been an optional and commonly well supported process step by most of foundriesto improve ESD robustness of the I/O devices. Device parameters such as the pinch-off voltage (V P ) and the zero-bias drain current (I DS0 ) of the proposed n-JFET device can be modified by adjusting the P+ separation (L) in the layout. With the adjustable pinch-off voltages, this device can be used for different circuit applications. The 2-D device simulations with technology computer aided design are used to analyze the depletion region and to verify the pinch-off voltage under different L values. The pinch-off voltage remains almost unchanged with the temperature variations. In addition, SPICE simulation results show good agreement with the experimental silicon (Si) data in term of I D -V D and I D -V G .