Details

Autor(en) / Beteiligte

• Chai, Tai Chong
• Zhang, Xiaowu
• Lau, John H
• Selvanayagam, Cheryl S
• Damaruganath, Pinjala
• Hoe, Yen Yi Germaine
• Ong, Yue Ying
• Rao, Vempati Srinivas
• Wai, Eva
• Li, Hong Yu
• Liao, E. Bin
• Ranganathan, Nagarajan
• Vaidyanathan, Kripesh
• Liu, Shiguo
• Sun, Jiangyan
• Ravi, Mullapudi
• Vath, Charles J
• Tsutsumi, Yoshihiro

Titel

Development of Large Die Fine-Pitch Cu/Low-[Formula Omitted] FCBGA Package With Through Silicon via (TSV) Interposer

Ist Teil von

• IEEE transactions on components, packaging, and manufacturing technology (2011), 2011-05, Vol.1 (5), p.660

Ort / Verlag

Piscataway: The Institute of Electrical and Electronics Engineers, Inc. (IEEE)

Erscheinungsjahr

2011

Quelle

IEEE Xplore

Beschreibungen/Notizen

• The continuous push for smaller bump pitch interconnection in line with smaller Cu/low-[Formula Omitted] technology nodes demands the substrate technology to support finer interconnection. However, the conventional organic buildup substrate is facing a bottleneck in fine-pitch wiring due to its technology limitation, and the cost of fabricating finer pitch organic substrate is higher. To address these needs, Si interposer with through silicon via (TSV) has emerged as a good solution to provide high wiring density interconnection, and at the same time to minimize coefficient of thermal expansion mismatch to the Cu/low-[Formula Omitted] chip that is vulnerable to thermal-mechanical stress and improve electrical performance due to shorter interconnection from the chip to the substrate. This paper presents the development of TSV interposer technology for a 21[Formula Omitted]21 mm Cu/low-[Formula Omitted] test chip on flip chip ball grid array (FCBGA) package. The Cu/low-[Formula Omitted] chip is a 65-nm nine-metal layer chip with 150-[Formula Omitted] SnAg bump pitch of total 11 000 I/O, with via chain and daisy chain for interconnect integrity monitoring and reliability testing. The TSV interposer size is 25[Formula Omitted]25[Formula Omitted]0.3 mm with CuNiAu as under bump metallization on the top side and SnAgCu bumps on the underside. The conventional bismaleimide triazine substrate size is 45[Formula Omitted]45 mm with BGA pad pitch of 1 mm and core thickness of 0.8 mm. Mechanical and thermal modeling and simulation for the FCBGA package with TSV interposer have been performed. TSV interposer fabrication processes and assembly process of the large die mounted on TSV interposer with Pb-free solder bumps and underfill have been set up. The FCBGA samples have passed moisture sensitivity test and thermal cycling reliability testing without failures in underfill delamination and daisy chain resistance measurements.