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A modified Bosch process is used to reduce leakage current resulting from surface damage and roughness for high aspect ratio pillars fabricated from Si p-i-n structures. C 4 F 8 is used during both the etch and passivation steps to achieve a scallop-free and vertical structure. A 5× decrease in both the reverse bias leakage current and corresponding improvement in effective carrier density, charge density, depletion width, and minority carrier lifetime are observed using this process, indicating that surface charge states are decreased using this process. This can impact a number of 3-D next-generation devices.