IEEE journal of solid-state circuits, 2011-10, Vol.46 (10), p.2396-2405
2011
Volltextzugriff (PDF)
Details
- Autor(en) / Beteiligte
- Titel
- Simultaneous Reverse Body and Negative Word-Line Biasing Control Scheme for Leakage Reduction of DRAM
- Ist Teil von
- IEEE journal of solid-state circuits, 2011-10, Vol.46 (10), p.2396-2405
- Ort / Verlag
- New York, NY: IEEE
- Erscheinungsjahr
- 2011
- Quelle
- IEEE Electronic Library Online
- Beschreibungen/Notizen
- In this paper, a simultaneous body and word-line biasing control scheme is described for minimizing the cell leakage current in DRAMs. In the proposed biasing scheme, both the reverse body and negative word-line bias voltages are simultaneously controlled in real time by monitoring the leakage current of a group of replica DRAM cells in different leakage conditions. Experimental results in a 46 nm DRAM technology indicated that the data retention time provided by the proposed scheme is improved by up to 60% as compared to the conventional fixed biasing scheme. They also indicated that the number of failure bits of a DRAM array was substantially reduced by adopting the proposed scheme.
- Sprache
- Englisch
- Identifikatoren
- ISSN: 0018-9200eISSN: 1558-173XDOI: 10.1109/JSSC.2011.2162184Titel-ID: cdi_pascalfrancis_primary_24776221
- Format
- –
- Schlagworte
- Applied sciences, Computer architecture, Data retention time, Design. Technologies. Operation analysis. Testing, Electronics, Exact sciences and technology, gate-induced drain leakage, Integrated circuits, Integrated circuits by function (including memories and processors), Junctions, Leakage current, Logic gates, negative word-line biasing, Random access memory, reverse body biasing, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, sub-threshold leakage, Threshold voltage, Transistors