IEEE journal of solid-state circuits, 2010-01, Vol.45 (1), p.111-119
2010
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Details
- Autor(en) / Beteiligte
- Titel
- 8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology
- Ist Teil von
- IEEE journal of solid-state circuits, 2010-01, Vol.45 (1), p.111-119
- Ort / Verlag
- New York, NY: IEEE
- Erscheinungsjahr
- 2010
- Quelle
- IEEE Electronic Library (IEL)
- Beschreibungen/Notizen
- An 8 Gb 4-stack 3-D DDR3 DRAM with through-Si-via is presented which overcomes the limits of conventional modules. A master-slave architecture is proposed which decreases the standby and active power by 50 and 25%, respectively. It also increases the I/O speed to > 1600 Mb/s for 4 rank/module and 2 module/channel case since the master isolates all chip I/O loadings from the channel. Statistical analysis shows that the proposed TSV check and repair scheme can increase the assembly yield up to 98%. By providing extra VDD/VSS edge pads, power noise is reduced to < 100 mV even if all 4 ranks are refreshed every clock cycle consecutively.
- Sprache
- Englisch
- Identifikatoren
- ISSN: 0018-9200eISSN: 1558-173XDOI: 10.1109/JSSC.2009.2034408Titel-ID: cdi_pascalfrancis_primary_22492659
- Format
- –
- Schlagworte
- 3-D architecture, Applied sciences, Assembly, assembly yield, CMOS logic circuits, CMOS technology, connectivity check and repair, DDR3 DRAM, double data rate, Electronics, Exact sciences and technology, gapless read, Integrated circuit interconnections, Integrated circuits, Integrated circuits by function (including memories and processors), master, Master-slave, module, Noise reduction, power edge pads, power noise reduction, Random access memory, rank, refresh, seamless, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, slave, stack, Statistical analysis, Sun, three dimensional, Through-silicon vias, Through-silicon-via (TSV), via first, via last, via middle