Sie befinden Sich nicht im Netzwerk der Universität Paderborn. Der Zugriff auf elektronische Ressourcen ist gegebenenfalls nur via VPN oder Shibboleth (DFN-AAI) möglich. mehr Informationen...
4 Gb/s/pin 32 bit 512 Mb GDDR4 (Graphics Double Data Rate 4) SDRAM was implemented by using an 80 nm CMOS process. It employs a data bus inversion (DBI) coding to overcome the bottleneck of a parallel single-ended signaling, a power consumption of I/O, power supply noise, and crosstalk. Both DBI AC and DC modes are combined to a single circuit by eliminating the feedback path of a conventional DBI AC circuit while achieving high-speed operation. The proposed DBI circuit uses an analog majority voter insensitive to mismatch for small area and delay. R on middot tuning further improves the voltage and time margin by adding a user-supplied offset to auto-calibrated R on middot. In addition, a dual duty cycle corrector (DCC) is used to reduce duty error and jitter by averaging two outputs of two DCCs. Measured results show that DBI DC coding reduces the peak-to-peak jitter from 65.5 ps to 44.5 ps and the voltage fluctuation from 183 mV to 115 mV at the data rate of 4 Gb/s with the 2 V.