Details

Autor(en) / Beteiligte

• Hafed, M.M.
• Chan, A.H.
• Duerden, G.
• Pishdad, B.
• Tam, C.
• Laberge, S.
• Roberts, G.W.

Titel

A high-throughput 5 Gbps timing and jitter test module featuring localized processing

Ist Teil von

• 2004 International Conferce on Test, 2004, p.728-737

Ort / Verlag

Piscataway NJ: IEEE

Erscheinungsjahr

2004

Link zum Volltext

• IEEE_Xplore

Quelle

IEEE Xplore

Beschreibungen/Notizen

• A compact timing and jitter test system that leverages custom integrated circuit measurement methods and localized test result processing is presented. It consists of five timing measurement units (TMU) and five timing generation units (TGU) as well as hardware digital processing units for local test result processing or parameter extraction. The TMU channels rely on a component-invariant vernier-delay measurement circuit and the TGU channels rely on linear programmable delay circuitry. The system supports both LVDS and CML highspeed digital interface standards at rates of up to 5 Gbps. This solution occupies 3"/spl times/4" of board area, which makes it suitable for placement on the DUT-board. It has a relative delay generation resolution of 3 ps at 5 Gbps, and is capable of autonomous, platform-independent pass-fail testing.