2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519), 2004, p.100-516 Vol.1
First edition, 2004
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Details
- Autor(en) / Beteiligte
- Titel
- A CMOS dual-band fractional-n synthesizer with reference doubler and compensated charge pump
- Ist Teil von
- 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519), 2004, p.100-516 Vol.1
- Auflage
- First edition
- Ort / Verlag
- Piscataway, New Jersey: IEEE
- Erscheinungsjahr
- 2004
- Quelle
- IEEE Xplore
- Beschreibungen/Notizen
- A fully integrated dual-band frequency synthesizer in 0.35 /spl mu/m CMOS technology achieves a phase noise of -141 dBc/Hz at 1.25 MHz offset in the PCS band with a reference frequency doubler. Fractional spurs are reduced by 8.6 dB at 50 kHz offset with a replica compensated charge pump.
- Sprache
- Englisch
- Identifikatoren
- ISBN: 0780382676, 9780780382671ISSN: 0193-6530eISSN: 2376-8606DOI: 10.1109/ISSCC.2004.1332613Titel-ID: cdi_pascalfrancis_primary_17457678
- Format
- –
- Schlagworte
- 1f noise, Applied sciences, Charge pumps, Circuit properties, Design. Technologies. Operation analysis. Testing, Dual band, Electric, optical and optoelectronic circuits, Electronic circuits, Electronics, Exact sciences and technology, Frequency, Integrated circuits, Phase locked loops, Phase noise, Quantization, Sampling methods, Semiconductor device noise, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Signal convertors, Synthesizers