Details

Autor(en) / Beteiligte

• Staszewski, R.B.
• Muhammad, K.
• Leipold, D.
• Chih-Ming Hung
• Yo-Chuol Ho
• Wallberg, J.L.
• Fernando, C.
• Maggio, K.
• Staszewski, R.
• Jung, T.
• Jinseok Koh
• John, S.
• Irene Yuanying Deng
• Sarda, V.
• Moreira-Tamayo, O.
• Mayega, V.
• Katz, R.
• Friedman, O.
• Eliezer, O.E.
• de-Obaldia, E.
• Balsara, P.T.

Titel

All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS

Ist Teil von

• IEEE journal of solid-state circuits, 2004-12, Vol.39 (12), p.2278-2291

Ort / Verlag

New York, NY: IEEE

Erscheinungsjahr

2004

Quelle

IEEE Xplore

Beschreibungen/Notizen

• We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The transceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter, respectively. The transmitter architecture takes advantage of the wideband frequency modulation capability of the all-digital phase-locked loop with built-in automatic compensation to ensure modulation accuracy. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The complete chip also integrates power management functions and a digital baseband processor. Application of the presented ideas has resulted in significant area and power savings while producing structures that are amenable to migration to more advanced deep-submicron processes, as they become available. The entire IC occupies 10 mm/sup 2/ and consumes 28 mA during transmit and 41 mA during receive at 1.5-V supply.