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Low-autocorrelation binary sequences: On improved merit factors and runtime predictions to achieve them

Applied soft computing, 2017-07, Vol.56, p.262-285

2017

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Design of experiments and evaluation of BDD ordering heuristics

International journal on software tools for technology transfer, 2001-05, Vol.3 (2), p.193-206

2001

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On Uncensored Mean First-Passage-Time Performance Experiments with Multi-Walk: a New Stochastic Optimization Algorithm

2018 7th International Conference on Reliability, Infocom Technologies and Optimization (Trends and Future Directions) (ICRITO), 2018, p.1-6

Brglez, Franc

2018

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A Local Search SAT Solver Using an Effective Switching Strategy and an Efficient Unit Propagation

Lecture notes in computer science, 2004, p.53-68

2004

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Performance testing of combinatorial solvers with isomorph class instances

Proceedings of the 2007 workshop on experimental computer science, 2007, p.13-es

2007

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Heuristics, Experimental Subjects, and Treatment Evaluation in Bigraph Crossing Minimization

The ACM journal of experimental algorithmics, 2001-12, Vol.6, p.8-es

2001

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On asymptotic complexity of the optimum Golomb ruler problem: From established stochastic methods to self-avoiding walks

2017 IEEE Congress on Evolutionary Computation (CEC), 2017, p.1000-1007

2017

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On SAT instance classes and a method for reliable performance experiments with SAT solvers

Annals of mathematics and artificial intelligence, 2005-01, Vol.43 (1-4), p.1-34

2005

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A universal client for distributed networked design and computing

Annual ACM IEEE Design Automation Conference: Proceedings of the 38th conference on Design automation, 2001, p.401-406

2001

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Heuristics and Experimental Design for Bigraph Crossing Number Minimization

Algorithm Engineering and Experimentation, 1999, p.74-93

1999

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Effective bounding techniques for solving unate and binate covering problems

Annual ACM IEEE Design Automation Conference: Proceedings of the 42nd annual conference on Design automation; 13-17 June 2005, 2005, p.385-390

2005

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Executable workflows: a paradigm for collaborative design on the Internet

Annual ACM IEEE Design Automation Conference: Proceedings of the 34th annual conference on Design automation; 09-13 June 1997, 1997, p.553-558

1997

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Design of Experiments for Evaluation of BDD Packages Using Controlled Circuit Mutations

Formal Methods in Computer-Aided Design, 2002, p.64-81

2002

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Effects of resource sharing on circuit delay: an assignment algorithm for clock period optimization

ACM transactions on design automation of electronic systems, 1998-04, Vol.3 (2), p.285-307

1998

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Fast true delay estimation during high level synthesis

IEEE transactions on computer-aided design of integrated circuits and systems, 1996-09, Vol.15 (9), p.1088-1105

1996

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Executable Workflows: A Paradigm For Collaborative Design On The Internet

Proceedings of the 34th Design Automation Conference, 1997, p.553-558

1997

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Transformations and resynthesis for testability of RT-level control-data path specifications

IEEE transactions on very large scale integration (VLSI) systems, 1993-09, Vol.1 (3), p.304-318

1993

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Synthesis of wiring signature-invariant equivalence class circuit mutants and applications to benchmarking

Proceedings Design, Automation and Test in Europe, 1998, p.656-663

1998

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Circuit partitioning for logic synthesis

IEEE journal of solid-state circuits, 1991-03, Vol.26 (3), p.350-363

1991

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Multi-way netlist partitioning into heterogeneous FPGAs and minimization of total device cost and interconnect

Annual ACM IEEE Design Automation Conference: Proceedings of the 31st annual conference on Design automation; 06-10 June 1994, 1994, p.238-243

1994

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Performance analysis and optimization of schedules for conditional and loop-intensive specifications

31st Design Automation Conference, 1994, p.491-496

1994

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Rapid prototyping of ASICs with OASIS: An open architecture silicon implementation software

SIGDA newsletter, 1991-06, Vol.21 (1), p.77-80

Brglez, Franc

1991

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Cost minimization of partitions into multiple devices

Annual ACM IEEE Design Automation Conference: Proceedings of the 30th international conference on Design automation; 14-18 June 1993, 1993, p.315-320

1993

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The scientific method and design and test

IEEE design & test of computers, 2000-07, Vol.17 (3), p.144-143

Brglez, F.

2000

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High-contrast algorithm behavior: observation, hypothesis, and experimental design

Proceedings of the 2007 workshop on experimental computer science, 2007, p.12-es

2007

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Low-autocorrelation binary sequences: On improved merit factors and runtime predictions to achieve them

Design of experiments and evaluation of BDD ordering heuristics

On Uncensored Mean First-Passage-Time Performance Experiments with Multi-Walk: a New Stochastic Optimization Algorithm

A Local Search SAT Solver Using an Effective Switching Strategy and an Efficient Unit Propagation

Performance testing of combinatorial solvers with isomorph class instances

Heuristics, Experimental Subjects, and Treatment Evaluation in Bigraph Crossing Minimization

On asymptotic complexity of the optimum Golomb ruler problem: From established stochastic methods to self-avoiding walks

On SAT instance classes and a method for reliable performance experiments with SAT solvers

A universal client for distributed networked design and computing

Heuristics and Experimental Design for Bigraph Crossing Number Minimization

Effective bounding techniques for solving unate and binate covering problems

Executable workflows: a paradigm for collaborative design on the Internet

Design of Experiments for Evaluation of BDD Packages Using Controlled Circuit Mutations

Effects of resource sharing on circuit delay: an assignment algorithm for clock period optimization

Fast true delay estimation during high level synthesis

Executable Workflows: A Paradigm For Collaborative Design On The Internet

Transformations and resynthesis for testability of RT-level control-data path specifications

Synthesis of wiring signature-invariant equivalence class circuit mutants and applications to benchmarking

Circuit partitioning for logic synthesis

Multi-way netlist partitioning into heterogeneous FPGAs and minimization of total device cost and interconnect

Performance analysis and optimization of schedules for conditional and loop-intensive specifications

Rapid prototyping of ASICs with OASIS: An open architecture silicon implementation software

Cost minimization of partitions into multiple devices

The scientific method and design and test

High-contrast algorithm behavior: observation, hypothesis, and experimental design

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