Electronics letters, 2018-04, Vol.54 (8), p.486-488
2018
Details
- Autor(en) / Beteiligte
- Titel
- Advanced layout techniques for high-speed analogue circuits in 28 nm HKMG CMOS process
- Ist Teil von
- Electronics letters, 2018-04, Vol.54 (8), p.486-488
- Ort / Verlag
- The Institution of Engineering and Technology
- Erscheinungsjahr
- 2018
- Link zum Volltext
- Quelle
- Wiley Blackwell Single Titles
- Beschreibungen/Notizen
- The effect of optimising the transistor finger width on the performance of high-speed analogue circuits in deep sub-micron processes is investigated, demonstrated in a 28 nm high-K/metal gate CMOS technology process. Silicon proven results demonstrate that the oscillator with a finger width of 440 nm gives the best performance based on the figure of merit (=142) among the benchmark design examples used.
- Sprache
- Englisch
- Identifikatoren
- ISSN: 0013-5194, 1350-911XeISSN: 1350-911XDOI: 10.1049/el.2017.4453Titel-ID: cdi_iet_journals_10_1049_el_2017_4453
- Format
- –
- Schlagworte
- advanced layout techniques, benchmark design, circuit optimisation, Circuits and systems, CMOS analogue integrated circuits, deep sub‐micron processes, figure of merit, high‐k dielectric thin films, high‐K‐metal gate CMOS technology process, high‐speed analogue circuits, high‐speed integrated circuits, HKMG CMOS process, integrated circuit layout, oscillator, oscillators, size 28 nm, size 440 nm, transistor circuits, transistor finger optimization effect