Details

Autor(en) / Beteiligte

• Zhao, Shulin
• Guo, Mingqiang
• Sin, Sai-Weng
• Qi, Liang
• Xu, Dengke
• Wang, Guoxing
• Martins, Rui P.

Titel

A 3.07mW 30MHz-BW 73.5dB-SNDR Time-Interleaved Noise-Shaping SAR ADC with 2nd-order Error-Feedforward and Redundancy-Bit Reduction

Ist Teil von

• 2022 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2022, p.1-3

Ort / Verlag

IEEE

Erscheinungsjahr

2022

Link zum Volltext

Quelle

IEEE Electronic Library (IEL)

Beschreibungen/Notizen

• The noise-shaping SAR (NS-SAR) combines the merits of the \Delta - \Sigma and the SAR ADCs, transforming it into an emerging ADC architecture to pull off high resolution and high power efficiency. However, the existing single-channel NS-SAR obtaining SNDR \gt 70 dB always suffers from bandwidth (BW) limitation <10 MHz due to the following reasons [1]: First, the settling time in the SAR's DAC increases significantly to meet high-resolution requirements with the large size of the CDAC. Besides, implementing a sharp noise transfer function (NTF) always involves residue amplification to compensate for the signal attenuation, which occupies a portion of time and leaves less time for SAR conversion.