Details

Autor(en) / Beteiligte

• Baghini, M.S.
• Desai, M.P.

Titel

Impact of technology scaling on metastability performance of CMOS synchronizing latches

Ist Teil von

• Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design, 2002, p.317-322

Ort / Verlag

IEEE

Erscheinungsjahr

2002

Quelle

IEEE Electronic Library (IEL)

Beschreibungen/Notizen

• In this paper, we use circuit simulations to characterize the effects of technology scaling on the metastability parameters of CMOS latches used as synchronizers. We perform this characterization by obtaining a synchronization error probability curve from a histogram of the latch delay. The main metastability parameters of CMOS latches are /spl tau//sub m/ and T/sub w/. /spl tau//sub m/ is the exponential time constant of the rate of decay of metastability and T/sub w/ is effective metastability window size at a normal propagation delay. Both parameters can be extracted from a histogram of the latch delay. This paper also explains a way to calibrate the simulator for accuracy. The simulations indicate that /spl tau//sub m/ scales better than the technology scale factor. T/sub w/ also scales down but its factor cannot be estimated as well as that of /spl tau//sub m/. This is because T/sub w/ is a complex function of signal and clock edge rate and logic threshold level.