Details

Autor(en) / Beteiligte

• Bufler, F. M.
• Arimura, H.
• Favia, P.
• Eneman, G.
• Matagne, P.
• Horiguchi, N.
• Hellings, G.

Titel

Monte Carlo Analysis of p-Type Si \text Ge \text -Channel Nanosheet Performance

Ist Teil von

• IEEE transactions on electron devices, 2022, p.1-4

Ort / Verlag

IEEE

Erscheinungsjahr

2022

Quelle

IEEE Electronic Library (IEL)

Beschreibungen/Notizen

• The performance of Si<inline-formula> <tex-math notation="LaTeX">_\text{0.75}</tex-math> </inline-formula>Ge<inline-formula> <tex-math notation="LaTeX">_\text{0.25}</tex-math> </inline-formula>-channel p -type nanosheet (NS) devices with a gate length of 14 nm and a sheet width of 12 nm is investigated by Monte Carlo (MC) device simulation. It is found that the stress in the Si-Ge channel can eliminate the performance imbalance with n -type NSs arising from the (001) surface in the absence of stress. The performance is the same as the theoretical performance of Si-channel (cSi) p -type NSs with Si<inline-formula> <tex-math notation="LaTeX">_\text{0.5}</tex-math> </inline-formula>Ge<inline-formula> <tex-math notation="LaTeX">_\text{0.5}</tex-math> </inline-formula> source/drain (S/D) pockets under the ideal assumption that no stress relaxation, e.g., due to grain boundaries from merging epitaxial growth occurs for the cSi devices. It is shown that the performance levels can be related to stress-induced quasi-ballistic velocity overshoot and the impact of alloy scattering. This is not captured by standard drift-diffusion (DD) simulation where a smaller saturation velocity predicts a performance degradation for Si-Ge channel devices.