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Study on Single-Event Gate Rapture of Si VDMOSFET: failure mechanism and influence factors
Ist Teil von
2022 23rd International Conference on Electronic Packaging Technology (ICEPT), 2022, p.1-4
Ort / Verlag
IEEE
Erscheinungsjahr
2022
Link zum Volltext
Quelle
IEEE Xplore Digital Library
Beschreibungen/Notizen
In this paper, the failure mechanism and influence factors of SEGR in Si VDMOSFET are investigated by using TCAD simulation. The results show that linear energy transfer (LET), gate applied voltage, incident point, incident angle, and gate dielectric material are critical factors. SEGR will occur if the superimposed electric field intensity in the gate dielectric layer is large enough. The possibility of SEGR will appear with increment of LET and gate applied negative voltage while it can be improved using high dielectric constant (high-K) materials, which may contribute to the SEGR hardened structure design of Si VDMOSFET. The risk of SEGR is the highest when particle enters the Si VDMOSFET perpendicularly from the middle of the gate which is the most sensitive region of triggering SEGR.