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We study Positive-Bias Temperature Instability (PBTI) of enhancement-mode Schottky Type p-GaN gate HEMTs with different gate stack geometry. In particular, we experimentally investigate the impact of the gate offset, the portion of the p-GaN layer in the gate stack that is not contacted by the gate metal. Our study reveals trapping-induced negative threshold voltage shifts after benign gate stress that are recoverable, consistent with the literature. At very high gate stress voltages, there is a permanent negative threshold shift consistent with a leakier gate-metal/p-GaN junction. However, for long gate offset length devices, a new PBTI mechanism with a permanent positive threshold shift arises at high gate stress voltages that is uniquely associated with the uncontacted offset region of the p-GaN layer. This implies that there is a trade-off between increasing the gate offset length to limit sidewall leakage and ensuring stable device performance. Our study further reveals the role that gate current continuity across both barriers in the gate stack of a p-GaN HEMT plays in setting up the gate electrostatics.