Details

Autor(en) / Beteiligte

• Kim, Moosung
• Yun, Sung Won
• Park, Jungjune
• Park, Hyun Kook
• Lee, Jungyu
• Kim, Yeong Seon
• Na, Daehoon
• Choi, Sara
• Song, Youngsun
• Lee, Jonghoon
• Yoon, Hyunjun
• Lee, Kangbin
• Jeong, Byunghoon
• Kim, Sanglok
• Park, Junhong
• Lee, Cheon An
• Lee, Jaeyun
• Lee, Jisang
• Chun, Jin Young
• Jang, Joonsuc
• Yang, Younghwi
• Moon, Seung Hyun
• Choi, Myunghoon
• Kim, Wontae
• Kim, Jungsoo
• Yoon, Seokmin
• Kwak, Pansuk
• Lee, Myunghun
• Song, Raehyun
• Kim, Sunghoon
• Yoon, Chiweon
• Kang, Dongku
• Lee, Jin-Yub
• Song, Jaihyuk

Titel

A 1Tb 3b/Cell 8th-Generation 3D-NAND Flash Memory with 164MB/s Write Throughput and a 2.4Gb/s Interface

Ist Teil von

• 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, Vol.65, p.136-137

Ort / Verlag

IEEE

Erscheinungsjahr

2022

Quelle

IEEE Xplore

Beschreibungen/Notizen

• As data sizes increase exponentially, the demand for higher-density NAND with a smaller cell size and a higher interface speed has also increased [1]-[4]. However, the increased number of WL-stack layers results in a smaller sensing circuit size and a smaller WL-to-WL spacing, which increases the intrinsic transistor variation and the inter-cell interference. One way to achieve good density while maintaining system performance is to support more multiple-plane operations with a circuit under cell array architecture, which leads to an increased noise power. Moreover, to achieve a 2.4Gb/s the I/O circuits need to support the faster speed while achieving lower power consumption. This paper presents the offset cancelling sensing latch (OCSL) scheme, the quad-group interference-free read (Q-IFR) scheme, and the common-source line (CSL) noise-tracking scheme to resolve the aforementioned challenges. In terms of the high-speed I/O bandwidth, a receiver circuit and an internal reference voltage generator are also proposed to increase the I/O speed, reduce the standby power consumption, and reduce the settling time when the chip is enabled.