Details

Autor(en) / Beteiligte

• Maneux, C.
• Mukherjee, C.
• Deng, M.
• Dubourg, M.
• Reveil, L.
• Bordea, G.
• Lecestre, A.
• Larrieu, G.
• Trommer, J.
• Breyer, E.T.
• Slesazeck, S.
• Mikolajick, T.
• Baumgartner, O.
• Karner, M.
• Pirker, D.
• Stanojevic, Z.
• Atienza, David
• Levisse, A.
• Ansaloni, G.
• Poittevin, A.
• Bosio, A.
• Deleruyelle, D.
• Marchand, C.
• O'Connor, I.

Titel

Modelling of vertical and ferroelectric junctionless technology for efficient 3D neural network compute cube dedicated to embedded artificial intelligence

Ist Teil von

• 2021 IEEE International Electron Devices Meeting (IEDM), 2021, p.15.6.1-15.6.4

Ort / Verlag

IEEE

Erscheinungsjahr

2021

Quelle

IEEE Electronic Library (IEL)

Beschreibungen/Notizen

• This paper presents the set of simulation means used to develop the concept of N 2 C 2 (neural network compute cube) based on a vertical transistor technology platform. On the basis of state-of-the-art junctionless nanowire transistors (JLNT), TCAD simulation, compact modeling and EM simulation are leveraged through a Design-Technology Co-Optimization (DTCO) to achieve innovative 3D circuit architectures. Further, System-Technology Co-Optimization (STCO) implications on 3D NN system architecture are explored.