Details

Autor(en) / Beteiligte

• Liu, Yu-Heng
• Yang, Yu-Siang
• Tseng, Chih-Yuan
• Lin, Wei
• Liu, An-Chang
• Hsu, Yu-Cheng

Titel

Triple-Level-Cell/Single-Level-Cell Mix-Mode Operation Induced Data Retention Degradation in 3-D NAND Flash Memories

Ist Teil von

• IEEE electron device letters, 2021-12, Vol.42 (12), p.1762-1765

Ort / Verlag

New York: IEEE

Erscheinungsjahr

2021

Quelle

IEEE Xplore

Beschreibungen/Notizen

• Compared to single-level-cell (SLC) mode operation, triple-level-cell (TLC) mode operation reduce NAND Flash lifetime due to its stronger program<inline-formula> <tex-math notation="LaTeX">/ </tex-math></inline-formula>erase (<inline-formula> <tex-math notation="LaTeX">\text{P}/\text{E} </tex-math></inline-formula>) cycled-induced oxide degradation and narrower read margin between neighboring states. However, by measuring the evolution characteristics of raw bit error rate (RBER) and threshold voltage (<inline-formula> <tex-math notation="LaTeX">\text{V}_{\text {t}} </tex-math></inline-formula>) shift during retention bake, TLC-erase <inline-formula> <tex-math notation="LaTeX">/ </tex-math></inline-formula>SLC-program mix-mode <inline-formula> <tex-math notation="LaTeX">\text{P}/\text{E} </tex-math></inline-formula> sequences in 3-D NAND Flash memory exhibits significant retention deterioration compared with pure TLC-mode <inline-formula> <tex-math notation="LaTeX">\text{P}/\text{E} </tex-math></inline-formula> schemes. Based on our measurement results, mix-mode operation may create more residual holes in the inter-gate spacing (IGS) region, giving rise to enhanced lateral migration of trapped charge in silicon nitride (SiN) storage layer and the larger <inline-formula> <tex-math notation="LaTeX">\text{V}_{\text {t}} </tex-math></inline-formula> retention loss accordingly.