Details

Autor(en) / Beteiligte

• Oka, M.
• Namba, Y.
• Sato, Y.
• Uchida, H.
• Doi, T.
• Tatsuno, T.
• Nakazawa, M.
• Tamura, A.
• Haga, R.
• Kuroda, M.
• Hosomi, M.
• Suemitsu, K.
• Kariyada, E.
• Suzuki, T.
• Tanigawa, H.
• Ueki, M.
• Moritoki, M.
• Takegawa, Y.
• Bessho, K.
• Umebayashi, T.

Titel

3D stacked CIS compatible 40nm embedded STT-MRAM for buffer memory

Ist Teil von

• 2021 Symposium on VLSI Technology, 2021, p.1-2

Ort / Verlag

Japan Society of Applied Physics (JSAP)

Erscheinungsjahr

2021

Quelle

IEEE Xplore

Beschreibungen/Notizen

• This paper presents the world's first demonstration of a 40nm embedded STT-MRAM for buffer memory, which is compatible with the 3D stacked CMOS image sensor (CIS) process. We optimized a CoFeB-based perpendicular magnetic tunnel junction (p-MTJ) to suppress the degradation of magnetic properties caused by the 3D stacked wafer process. With improved processes, we achieved high speed write operation below 40 ns under typical operation voltage conditions at -30 °C, endurance up to 1E+10 cycles at 105 °C and 1 s data retention at 85 °C required for a buffer memory. In addition, to broaden the application of embedded MRAM (eMRAM), we proposed a novel fusion technology that integrated embedded non-volatile memory (eNVM) and buffer memory type embedded MRAM in the same chip. We achieved a data retention of 1 s ~ >10 years with a sufficient write margin using the fusion technology.