Details

Autor(en) / Beteiligte

• Tong, Xingyuan
• Wu, Jinwu
• Chen, Dong

Titel

Low-Phase-Error Small-Area 4-Phase DLL With a Single-Ended-Differential-Single-Ended Voltage-Controlled Delay Line

Ist Teil von

• IEEE transactions on circuits and systems. II, Express briefs, 2022-01, Vol.69 (1), p.25-29

Ort / Verlag

New York: IEEE

Erscheinungsjahr

2022

Quelle

IEEE Electronic Library Online

Beschreibungen/Notizen

• In this brief, a four-phase delay-locked loop (DLL) with low phase error, low power consumption, and small area is presented for time-to-digital conversion application. A highly matched single-ended differential single-ended voltage-controlled delay line is proposed to improve the phase uniformity of these multiple output signals. A digital auxiliary duty-cycle corrector is designed to adjust the width of the output signal to reduce the pulse width error and to make the duty cycle of each output signal approximately 50%. Designed using 0.18-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> CMOS technology, this DLL occupies an active area of 111.32 <inline-formula> <tex-math notation="LaTeX">\mu \text{m}\,\,\times </tex-math></inline-formula> 82.74 <inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula>. With a 1.8 V supply voltage and a 250 MHz operating frequency, the measured power consumption and output phase error rate of this DLL are 2.28 mW and 1.3%, respectively.