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IEEE transactions on very large scale integration (VLSI) systems, 2021-06, Vol.29 (6), p.1244-1256
2021

Details

Autor(en) / Beteiligte
Titel
Enabling Write-Reduction Multiversion Scheme With Efficient Dual-Range Query Over NVRAM
Ist Teil von
  • IEEE transactions on very large scale integration (VLSI) systems, 2021-06, Vol.29 (6), p.1244-1256
Ort / Verlag
New York: IEEE
Erscheinungsjahr
2021
Link zum Volltext
Quelle
IEEE/IET Electronic Library (IEL)
Beschreibungen/Notizen
  • Due to cyber-physical systems, a large-scale multiversion indexing scheme has garnered significant attention in recent years. However, modern multiversion indexing schemes have significant drawbacks (e.g., heavy write traffic and weak key- or version-range-query performance) while being applied to a computer system with a nonvolatile random access memory (NVRAM) as its main memory. Unfortunately, with the considerations of high memory cell density and zero-static power consumption, NVRAM has been regarded as a promising candidate to substitute for dynamic random access memory (DRAM) in future computer systems. Therefore, it is critical to make a multiversion indexing scheme friendly for an NVRAM-based system. For tackling this issue with modern multiversion indexing schemes, this article proposes a write-reduction multiversion indexing scheme with efficient dual-range queries. According to the experiments, our scheme effectively reduces the amount of write traffic generated by the multiversion indexing scheme to NVRAM. It offers efficient dual-range queries by consolidating the proposed version forest and the multiversion tree.

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