Details

Autor(en) / Beteiligte

• Zhang, Cong
• Liu, Dongsheng
• Liu, Xingjie
• Zou, Xuecheng
• Niu, Guangda
• Liu, Bo
• Jiang, Quming

Titel

Towards Efficient Hardware Implementation of NTT for Kyber on FPGAs

Ist Teil von

• 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021, p.1-5

Ort / Verlag

IEEE

Erscheinungsjahr

2021

Quelle

IEEE Xplore

Beschreibungen/Notizen

• Kyber is a promising lattice-based post-quantum cryptography (PQC) for key encapsulation mechanisms. Since number theoretic transform (NTT) is the most computationally expensive operation in Kyber, this paper focuses on novel optimization techniques for efficient hardware implementation of NTT for Kyber. Benefiting from the proposed fast modular multiplication method and a doubled bandwidth ping-pong memory access scheme, our NTT architecture can complete an NTT operation in Kyber in 490 cycles using only 609 LUTs, 640 FFs, 2 DSPs on a Xlinx Artix-7 FPGA. The proposed NTT architecture is 3.95 times faster than the state-of-the-art design for Kyber while achieves an improvement of more than 1.5 times in the area time product (ATP). Compared with the state-of-the- art NTT designs for other algorithms, our NTT architecture reduces 24% FFs and 50% DSPs and ranks second smallest in ATPs, which can also confirm the high efficiency of our design.