Details

Autor(en) / Beteiligte

• Cho, Jiho
• Kang, D. Chris
• Park, Jongyeol
• Nam, Sang-Wan
• Song, Jung-Ho
• Jung, Bong-Kil
• Lyu, Jaedoeg
• Lee, Hogil
• Kim, Won-Tae
• Jeon, Hongsoo
• Kim, Sunghoon
• Kim, In-Mo
• Son, Jae-Ick
• Kang, Kyoungtae
• Shim, Sang-Won
• Park, JongChul
• Lee, Eungsuk
• Kang, Kyung-Min
• Park, Sang-Won
• Lee, Jaeyun
• Moon, Seung Hyun
• Kwak, Pansuk
• Jeong, ByungHoon
• Lee, Cheon An
• Kim, Kisung
• Ko, Junyoung
• Kwon, Tae-Hong
• Lee, Junha
• Lee, Yohan
• Kim, Chaehoon
• Lee, Myeong-Woo
• Yun, Jeong-yun
• Lee, HoJun
• Choi, Yonghyuk
• Hong, Sanggi
• Park, JongHoon
• Shin, Yoonsung
• Kim, Hojoon
• Kim, Hansol
• Yoon, Chiweon
• Byeon, Dae Seok
• Lee, Seungjae
• Lee, Jin-Yub
• Song, Jaihyuk

Titel

30.3 A 512Gb 3b/Cell 7th -Generation 3D-NAND Flash Memory with 184MB/s Write Throughput and 2.0Gb/s Interface

Ist Teil von

• 2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, Vol.64, p.426-428

Ort / Verlag

IEEE

Erscheinungsjahr

2021

Quelle

IEEE Electronic Library Online

Beschreibungen/Notizen

• The exponential data size growth in high-speed networks is a key motivator for nonvolatile memory development. To support this demand, higher density NAND is required: with a smaller cell size and higher interface speed. Generally, scaling down NAND technology requires addressing several common issues: 1) As the number of WL stack layers increases, the cell-string current is reduced due to the increased resistance in a cell string, 2) Deterioration of cell-to-cell interference, due to the reduction of cell pitch, 3) Support of higher IO bandwidth for faster data transfer speed [1]. Another challenge of this work was to minimize the die size because the peripheral circuit area is comparable to that of the cell array. Hence, we integrated the peripheral circuits below the cell array as introduced in [2]. Also, to cope with lower metal-contact height, a novel structure for the capacitor device was used to maximize capacitance per unit area.