Details

Autor(en) / Beteiligte

• Hyunpil Noh
• Woncheol Cho
• Gucheol Jeong
• Min Huh
• Jaemin Ahn
• Ysung Kim
• Suock Jeong
• Seongjoon Lee
• Dongseok Kim
• Hazoong Kim
• Jaebuhm Suh
• Jinwon Park
• Sang-don Lee
• Hee-koo Yoon

Titel

A 0.115 /spl mu/m/sup 2/ 8F/sup 2/ DRAM working cell with LPRD (low parasitic resistance device) and poly metal gate technology for gigabit DRAM

Ist Teil von

• 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184), 2001, p.25-26

Ort / Verlag

IEEE

Erscheinungsjahr

2001

Link zum Volltext

• IEEE_Xplore

Quelle

IEEE Xplore

Beschreibungen/Notizen

• An 8F/sup 2/ stack DRAM cell, 0.115 /spl mu/m/sup 2/ in size, has been successfully integrated using a selective epitaxial plug scheme for landing plug contacts and poly metal gates and MIM COB capacitors, by which cell working has been proven under easy function check mode. The cell transistor exhibits sufficient saturation current (I/sub OP/) of >40 /spl mu/A with threshold voltage (V/sub tsat/) of 1.0 V.