Details

Autor(en) / Beteiligte

• Santhanam, S.
• Allmon, R.
• Anne, K.
• Blake, R.
• Bunger, N.
• Campbell, B.
• Carlson, M.
• Zongjian Chen
• Cheng, J.
• Tuan Do
• Dobberpuhl, D.
• Ingino, J.
• Kidd, D.
• Kruckemyer, D.
• Jong Lee
• Murray, D.
• Nishimoto, S.
• O'Donnell, L.
• Oykher, M.
• Panich, M.
• Pearce, M.
• Priore, D.
• Rodriguez, D.
• Rogenmoser, R.
• Dongwook Suh
• Sundaresan, V.
• Supnet, E.
• Von Kaenel, V.
• Yee, G.
• Yiu, G.
• Vo, C.
• Wen, R.

Titel

A 1 GHz power efficient single chip multiprocessor system for broadband networking applications

Ist Teil von

• 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185), 2001, p.107-110

Ort / Verlag

IEEE

Erscheinungsjahr

2001

Quelle

IEEE Electronic Library (IEL)

Beschreibungen/Notizen

• The Broadcom BCM12500 is a high performance system on a chip (SOC) targeted at network centric tasks. The chip consists of two high performance SB-1 MIPS64/sup TM/ CPUs, a shared 512 KB L2 cache, a DDR memory controller, and integrated I/O. All major blocks of the processor are connected together via the ZBbus/sup TM/; a high speed split transaction fully coherent multi processor bus. Three Gigabit Ethernet MACs enable a direct interface to network elements. High-speed system I/O is provided using AMD's Lightning Data Transport (LDT/sup TM/) I/O fabric and a 66 MHz PCI bus. The die measures 14.2 mm by 13.3 mm in a bulk 0.15 /spl mu/m CMOS technology and has a power dissipation of 13 W at 1.2 V and 1 GHz.