Details

Autor(en) / Beteiligte

• Zhou, Hongtao
• Dou, Runjiang
• Yu, Shuangming
• Qi, Nan
• Liu, Jian
• Wu, Nanjian
• Liu, Liyuan

Titel

A High-Speed Parallel FPGA Implementation of Harris Corner Detection

Ist Teil von

• 2020 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA), 2020, p.71-72

Ort / Verlag

IEEE

Erscheinungsjahr

2020

Quelle

IEEE Xplore

Beschreibungen/Notizen

• Harris corner detection is a common operation in the field of image processing, but suffering from computation complexity in embedded system. The current method of corner detection is to process one pixel in one clock cycle. With the improvement of image acquisition method in modern society, higher processing speed requirements have been proposed for the implementation of corner detection. This paper presents a new pixel-level parallelism FPGA implementation for Harris corner detection, which double the processing speed or more with almost no decreasing in accuracy. It is implemented on FPGA in the high-speed camera, and the experimental results show that the implementation is suitable for real-time applications.