Details

Autor(en) / Beteiligte

• Ramm, P.
• Bonfert, D.
• Gieser, H.
• Haufe, J.
• Iberl, F.
• Klumpp, A.
• Kux, A.
• Wieland, R.

Titel

InterChip via technology for vertical system integration

Ist Teil von

• Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461), 2001, p.160-162

Ort / Verlag

IEEE

Erscheinungsjahr

2001

Quelle

IEEE/IET Electronic Library

Beschreibungen/Notizen

• Vertical System Integration VSI(R) means the realization of three-dimensional integrated systems by thinning, stacking and vertical interchip wiring of completely processed and electrically tested device substrates. The I_nterC_hip V_ia (ICV) technology is introduced and discussed as a fully CMOS-compatible wafer-scale process which provides vertical electrical interchip interconnects placed at arbitrary locations, without intervention to the IC's fabrication technologies. Thinning of the device substrate (150 mm) down to 10 /spl mu/m as well as bonding it to an other silicon wafer had basically no influence on the electrical performance of EEPROM-products and process monitor structures. Resistances of 2 /spl Omega/ for a 2/spl times/2 /spl mu/m/sup 2/ interchip via contact and working contact chains with 480 interchip via contacts are promising results for the future fabrication of multi-layered three-dimensional systems combining the advantages of different device technologies.