2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2020, p.1-8
2020
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Details
- Autor(en) / Beteiligte
- Titel
- DRAMA: an approximate DRAM architecture for high-performance and energy-efficient deep training system
- Ist Teil von
- 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2020, p.1-8
- Ort / Verlag
- New York, NY, USA: ACM
- Erscheinungsjahr
- 2020
- Quelle
- IEEE Xplore
- Beschreibungen/Notizen
- As the density of DRAM becomes larger, the refresh overhead becomes more significant. This becomes more problematic in the systems that require large DRAM capacity, such as the training of deep neural networks (DNNs). To solve this problem, we present DRAMA, a novel architecture which employs the approximate characteristic of DNNs. We make that non-critical bits are not refreshed while critical bits are normally refreshed. The refresh time of the critical bits are concealed by employing per-bank refreshes, significantly improving the training system performance. Furthermore, the potential racing hazard of bank-refresh technique is simply prevented by our novel command scheduler in DRAM controllers. Our experiments on various recent DNNs show that DRAMA can improve the training system performance by 10.4% and save 23.77% DRAM energy compared to the conventional architecture.
- Sprache
- Englisch
- Identifikatoren
- ISBN: 9781450380263, 1450380263eISSN: 1558-2434DOI: 10.1145/3400302.3415637Titel-ID: cdi_ieee_primary_9256445
- Format
- –
- Schlagworte
- Approximate Computing, approximate DRAM architecture, bank-refresh technique, command scheduler, Computer architecture, deep neural networks, DNNs, DRAM capacity, DRAM chips, DRAM controllers, DRAM refresh, DRAMA, energy-efficient deep training system, Hardware, Hardware -- Integrated circuits, Hardware -- Integrated circuits -- Semiconductor memory, Hardware -- Integrated circuits -- Semiconductor memory -- Dynamic memory, Hazards, high-performance deep training system, Memory Architecture, neural nets, Neural networks, power aware computing, Random access memory, scheduling, System performance, Training