Details

Autor(en) / Beteiligte

• Lin, Zhifeng
• Xie, Yanyue
• Qian, Gang
• Wang, Sifei
• Yu, Jun
• Chen, Jianli

Titel

Late Breaking Results: An Analytical Timing-Driven Placer for Heterogeneous FPGAs

Ist Teil von

• 2020 57th ACM/IEEE Design Automation Conference (DAC), 2020, p.1-2

Ort / Verlag

IEEE

Erscheinungsjahr

2020

Quelle

IEEE Electronic Library (IEL)

Beschreibungen/Notizen

• As the feature sizes keep shrinking, interconnect delays have become a major limiting factor for FPGA timing closure. Traditional placement algorithms that address wirelength alone are no longer sufficient to close timing, especially for the large-scale heterogeneous FPGAs. In this paper, we resolve the crucial FPGA placement problem by optimizing wirelength and timing simultaneously. First, a smoothed routing-architecture-aware timing model is proposed to accurately estimate each interconnect delay. Then, a timing-driven delay look-up table is constructed to further speed up delay access. Finally, we present an effective wirelength and timing co-optimization strategy to produce high-quality placements without timing violations. Compared with Vivado 2019.1 on Xilinx benchmark suites for xc7k325t device, experimental results show that our algorithm achieves not only a 6.6% improvement in worst slack but also a 3.2% reduction for routed wirelength.