Details

Autor(en) / Beteiligte

• Khattak, Muhammad Kashif
• Fahim, Hamza
• Majeed, Muhammad Faran
• Rehman, Eid
• Javaid, Shumaila

Titel

Lookaside: Augmenting the Performance of Packet Processing Pipeline

Ist Teil von

• IEEE systems journal, 2021-09, Vol.15 (3), p.3561-3564

Ort / Verlag

New York: IEEE

Erscheinungsjahr

2021

Quelle

IEEE Electronic Library (IEL)

Beschreibungen/Notizen

• The network switches and routers need to forward the network packets at a line-rate. The underlying hardware and software implementations may limit the performance of these packet processing devices. In this paper, we propose a novel model, called Lookaside , to increase the performance of the network switches by extracting the payload from the packet and storing it in a nearby standard memory, such as dynamic random access memory (DRAM), before the packet is sent for processing. We know that the packet payload has no role in packet processing. We implemented the prototypes of our Lookaside switch model on the state-of-the-art ONetSwitch45 hardware field-programmable gate array board. The simulation results show an increase in the performance of the switch in terms of latency, throughput, switching chip resources, and on-chip resources power consumption as compared to SimpleSwitch.