Details

Autor(en) / Beteiligte

• Hsu, Chen-Hao
• Hung, Shao-Chun
• Chen, Hao
• Sun, Fan-Keng
• Chang, Yao-Wen

Titel

A DAG-Based Algorithm for Obstacle-Aware Topology-Matching On-Track Bus Routing

Ist Teil von

• IEEE transactions on computer-aided design of integrated circuits and systems, 2021-03, Vol.40 (3), p.533-546

Ort / Verlag

New York: IEEE

Erscheinungsjahr

2021

Quelle

IEEE Electronic Library Online

Beschreibungen/Notizen

• As clock frequencies increase, topology-matching bus routing is desired to provide an initial routing result which facilitates the following buffer insertion to meet the timing constraints. In this article, we present a complete topology-matching bus routing framework considering nonuniform track configurations. In the framework, a bus clustering technique is proposed to reduce the routing complexity by grouping buses sharing similar pin locations. To perform topology-matching routing in a nonuniform track configuration, we propose a directed acyclic graph-based algorithm to connect a bus in a specific topology. Furthermore, a rip-up and reroute scheme is applied to alleviate the routing congestion. Compared with the state-of-the-art topology-matching bus routers, our proposed algorithm significantly improves the routing quality and reduces the number of spacing violations in comparable runtime.