Details

Autor(en) / Beteiligte

• Koziel, Brian
• Ackie, A-Bon
• Khatib, Rami El
• Azarderakhsh, Reza
• Kermani, Mehran Mozaffari

Titel

SIKE'd Up: Fast Hardware Architectures for Supersingular Isogeny Key Encapsulation

Ist Teil von

• IEEE transactions on circuits and systems. I, Regular papers, 2020-12, Vol.67 (12), p.4842-4854

Ort / Verlag

New York: IEEE

Erscheinungsjahr

2020

Quelle

IEEE

Beschreibungen/Notizen

• In this work, we present a fast parallel architecture to perform supersingular isogeny key encapsulation (SIKE). We propose and implement a fast isogeny accelerator architecture that uses fast and parallelized isogeny formulas. On top of our isogeny accelerator, we build a novel architecture for the SIKE primitive, which provides both quantum and IND-CCA security. We synthesized this architecture on the Xilinx Artix-7, Virtex-7, and Kintex UltraScale+ FPGA families. Over Virtex-7 FPGA's, our constant-time implementations are roughly 14% faster than the state-of-the-art with a better area-time product. At the NIST security level 5 on a Kintex UltraScale+ FPGA, we can execute the entire SIKE protocol in 15.3 ms. This work continues to improve the speed of isogeny-based computations and also features all parameter sets of the SIKE round 2 specification, with results applicable to NIST's post-quantum standardization process.