Details

Autor(en) / Beteiligte

• Kung, Ji Fu
• Kung, Yung Chien
• Lin, Jing Pei
• Chen, Ming Wei
• Chen, Te Hsuan
• Yang, Hsiao Ying
• Chen, Pei Wen

Titel

Mining Factors Impact Wafer Circuit Probing Via Neural Network and Statistics for Semiconductor Device Fabrication

Ist Teil von

• 2019 Joint International Symposium on e-Manufacturing & Design Collaboration(eMDC) & Semiconductor Manufacturing (ISSM), 2019, p.1-2

Ort / Verlag

Taiwan Semiconductor Industry Association

Erscheinungsjahr

2019

Link zum Volltext

Quelle

IEEE Electronic Library (IEL)

Beschreibungen/Notizen

• Wafer circuit probing (CP) testing is one of the most important processes for semiconductor manufacturing to ensure the wafers are of good quality. However, the outcomes of CP measurements are not always as good as expected. Engineers take lots of efforts to diagnose CP measurement and classify the features so that make the root cause more evident. In searching the root cause for low yield wafers, gathering the bad wafers and finding their correlation between yields and stages for each process is a common procedure to check whether the stage or the corresponding equipment is the one of the factors that lowers the yield significantly. A system was developed to realize the procedure that defines wafer status and points out the problems that make the yield lower. Once a wafer was inputted into this system, a diagnosis for the wafer will be made automatically. And hence this system was named auto commonality, which means grouping the bad wafers and finding the root cause then making decisions without any manpower.